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1-mbit (64k x 16) static ram cy7c1021cv33 cypress semiconductor corporation ? 3901 north first street ? san jose ? ca 95134 ? 408-943-2600 document #: 38-05132 rev. *d revised june 20, 2004 features ? temperature ranges ? commercial: 0c to 70c ? industrial: ?40c to 85c ? automotive: ?40c to 125c ? pin- and function-compatible with cy7c1021bv33 ?high speed ?t aa = 8 ns (commercial & industrial) ?t aa = 12 ns (automotive) ? cmos for optimum speed/power ? low active power: 360 mw (max.) ? automatic power-down when deselected ? independent control of upper and lower bits ? available in 44-pin tsop ii, 400-mil soj, 48-ball fbga ? also available in lead (pb)-free 44-pin tsop ii, 400-mil soj functional description [1] the cy7c1021cv33 is a high-performance cmos static ram organized as 65,536 words by 16 bits. this device has an automatic power-down featur e that significantly reduces power consumption when deselected. writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 1 through i/o 8 ), is written into the location specified on the address pins (a 0 through a 15 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 9 through i/o 16 ) is written into the location specified on the address pins (a 0 through a 15 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins will appear on i/o 1 to i/o 8 . if byte high enable (bhe ) is low, then data from memory will appear on i/o 9 to i/o 16 . see the truth table at the end of this data sheet for a complete description of read and write modes. the input/output pins (i/o 1 through i/o 16 ) are placed in a high-impedance state when the device is deselected (ce high), the outputs are disabled (oe high), the bhe and ble are disabled (bhe , ble high), or during a write operation (ce low, and we low). the cy7c1021cv33 is available in standard 44-pin tsop type ii, 400-mil-wide soj packages, as well as a 48-ball fbga. note: 1. for best-practice recommendations, please refer to the cypr ess application note ?system design guidelines? on http://www.cypr ess.com. logic block diagram 64k x 16 ram array i/o 1 ?i/o 8 row decoder a 7 a 6 a 5 a 4 a 3 a 0 column decoder a 9 a 10 a 11 a 12 a 13 a 14 a 15 512 x 2048 sense amps data in drivers oe a 2 a 1 i/o 9 ?i/o 16 ce we ble bhe a 8
cy7c1021cv33 document #: 38-05132 rev. *d page 2 of 13 pin configurations selection guide cy7c1021cv33 -8 cy7c1021cv33- 10 cy7c1021cv33- 12 cy7c1021cv33- 15 unit maximum access time 8 10 12 15 ns maximum operating current 95 90 85 80 ma automotive - - 90 - ma maximum cmos standby current 5555 ma automotive - - 10 - ma we pin configuration 1 2 3 4 5 6 7 8 9 10 11 14 31 32 36 35 34 33 37 40 39 38 top view soj / tsop ii 12 13 41 44 43 42 16 15 29 30 v cc a 15 a 14 a 13 a 12 nc a 4 a 3 oe v ss a 5 i/o 16 a 2 ce i/o 3 i/o 1 i/o 2 bhe nc a 1 a 0 18 17 20 19 i/o 4 27 28 25 26 22 21 23 24 nc v ss i/o 7 i/o 5 i/o 6 i/o 8 a 6 a 7 ble v cc i/o 15 i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 9 a 8 a 9 a 10 a 11 48-ball fbga we v cc a 11 a 10 nc a 6 a 0 a 3 ce i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe v ss a 7 i/o 0 bhe nc a 2 a 1 ble v cc i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 nc nc nc 3 2 6 5 4 1 d e b a c f g h (top view) nc nc
cy7c1021cv33 document #: 38-05132 rev. *d page 3 of 13 pin definitions pin name soj, tsop- pin number bga pin number i/o type description a 0 ?a 15 1?5, 18?21, 24?27, 42?44 a3, a4, a5, b3, b4, c3, c4, d4, h2, h3, h4, h5, g3, g4, f3, f4 input address inputs used to select one of the address locations . i/o 0 ?i/o 15 [2] 7?10, 13?16, 29?32, 35?38 b6, c6, c5, d5, e5, f5, f6, g6, b1, c1, c2, d2, e2, f2, f1, g1 input/output bidirectional data i/o lines . used as input or output lines depending on operation. nc 22, 23, 28 a6, d3, e3, e4, g2, h1, h6 no connect no connects . not connected to the die. we 17 g5 input/control write enable input, active low . when selected low, a write is conducted. when deselected high, a read is conducted. ce 6 b5 input/control chip enable input, active low . when low, selects the chip. when high, deselects the chip. bhe , ble 39, 40 a1, b2 input/control byte write select inputs, active low . ble controls i/o 8 ?i/o 1 , bhe controls i/o 16 ?i/o 9 . oe 41 a2 input/control output enable, active low . controls the direction of the i/o pins. when low, the i/o pins are allowed to behave as outputs. when deasserted high, i/o pins are three-stated, and act as input data pins. v ss 12,34 d1, e6 ground ground for the device . should be connected to ground of the system. v cc 11,33 d6, e1 power supply power supply inputs to the device. note: 2. i/o 1 ?i/o 16 for soj/tsop and i/o 0 ?i/o 15 for bga packages.
cy7c1021cv33 document #: 38-05132 rev. *d page 4 of 13 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ?65 c to +150 c ambient temperature with power applied............................................. ?55 c to +125 c supply voltage on v cc to relative gnd [3] .... ?0.5v to +4.6v dc voltage applied to outputs in high-z state [3] ......................................?0.5v to v cc +0.5v dc input voltage [3] ...................................?0.5v to v cc +0.5v current into outputs (low) .... .....................................20 ma static discharge voltage......... .............. .............. ....... >2001v (per mil-std-883, method 3015) latch-up current...................................................... >200 ma operating range range ambient temperature (t a )v cc commercial 0 c to +70 c 3.3v 10% industrial ?40 c to +85 c3.3v 10% automotive ?40 c to +125 c3.3v 10% electrical characteristics over the operating range parameter description test conditions 1021cv33-8 1021cv33-10 1021cv33-12 1021cv33-15 unit min. max. min. max. min. max. min. max. v oh output high voltage v cc = min., i oh = ?4.0 ma 2.4 2.4 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 0.4 0.4 v v ih input high voltage 2.0 v cc + 0.3 2.0 v cc + 0.3 2.0 v cc + 0.3 2.0 v cc + 0.3 v v il input low voltage [3] ?0.3 0.8 ? 0.3 0.8 ?0.3 0.8 ?0.3 0.8 v i ix input load current gnd < v i < v cc com?l / ind?l ? 1 + 1 ? 1+1?1+1?1+1 a automotive ?12 +12 a i oz output leakage current gnd < v i < v cc , output disabled com?l / ind?l ? 1 + 1 ? 1+1?1+1?1+1 a automotive - - - - ?12 +12 - - a i os output short circuit current [4] v cc = max., v out = gnd -300 ? 300 ?300 ?300 ma i cc v cc operating supply current v cc = max., i out = 0 ma, f = f max = 1/t rc com?l / ind?l 95 90 85 80 ma automotive - - 90 - ma i sb1 automatic ce power-down current ?ttl inputs max. v cc , ce > v ih v in > v ih or v in < v il , f = f max com?l / ind?l 15 15 15 15 ma automotive - - 20 - ma i sb2 automatic ce power-down current ?cmos inputs max. v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f = 0 com?l / ind?l 5 5 5 5 ma automotive - - 10 - ma notes: 3. v il (min.) = ?2.0v and v ih (max) = v cc + 0.5v for pulse durations of less than 20 ns. 4. not more than one output should be shorted at one time. duration of the short circuit should not exceed 30 seconds. 5. tested initially and after any design or process changes that may affect these parameters.
cy7c1021cv33 document #: 38-05132 rev. *d page 5 of 13 ac test loads and waveforms [6] note: 6. ac characteristics (except high-z) for all 8-ns parts are test ed using the load conditions shown in figure (a). all other spe eds are tested using the thevenin load shown in figure (b). high-z characteristics are tested fo r all speeds using the test load shown in figure (d). thermal resistance [5] parameter description test conditions 48-ball fbga 44-lead soj 44-lead tsop-ii unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia / jesd51. 95.32 65.06 76.92 c/w jc thermal resistance (junction to case) 10.68 34.21 15.86 c/w capacitance [5] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 8pf c out output capacitance 8 pf 90% 10% 3.0v gnd 90% 10% all input pulses 3.3v output 30 pf* * capacitive load consists of all components of the test environment (b) r 317 ? r2 351 ? rise time: 1 v/ns fall time: 1 v/ns 30 pf* output z = 50 ? 50 ? 1.5v (c) (a) 3.3v output 5 pf (d) r 317 ? r2 351 ? 8-ns devices: 10-, 12-, 15-ns devices: high-z characteristics:
cy7c1021cv33 document #: 38-05132 rev. *d page 6 of 13 switching characteristics over the operating range [7] parameter description 1021cv33-8 1021cv33-10 1021cv33-12 1021cv33-15 unit min. max. min. max. min. max. min. max. read cycle t rc read cycle time 8 10 12 15 ns t aa address to data valid 8 10 12 15 ns t oha data hold from address change 3 3 3 3 ns t ace ce low to data valid 8 10 12 15 ns t doe oe low to data valid 5 5 6 7 ns t lzoe oe low to low-z [8] 0000ns t hzoe oe high to high-z [8, 9] 4567ns t lzce ce low to low-z [8] 3333ns t hzce ce high to high-z [8, 9] 4567ns t pu [10] ce low to power-up 0 0 0 0 ns t pd [10] ce high to power-down 8 10 12 15 ns t dbe byte enable to data valid 5 5 6 7 ns t lzbe byte enable to low-z 0 0 0 0 ns t hzbe byte disable to high-z 4 5 6 7 ns write cycle [11] t wc write cycle time 8 10 12 15 ns t sce ce low to write end 7 8 9 10 ns t aw address set-up to write end 7 8 9 10 ns t ha address hold from write end 0 0 0 0 ns t sa address set-up to write start 0 0 0 0 ns t pwe we pulse width 6 7 8 10 ns t sd data set-up to write end 5 5 6 8 ns t hd data hold from write end 0 0 0 0 ns t lzwe we high to low-z [8] 3333ns t hzwe we low to high-z [8, 9] 4567ns t bw byte enable to end of write 6 7 8 9 ns notes: 7. test conditions assume signal transition ti me of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v. 8. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 9. t hzoe , t hzbe , t hzce , and t hzwe are specified with a load c apacitance of 5 pf as in part (d) of ac te st loads. transition is measured 500 mv from steady-state voltage. 10. this parameter is guaranteed by design and is not tested. 11. the internal write time of the me mory is defined by the overlap of ce low, we low and bhe /ble low. ce , we and bhe /ble must be low to initiate a write, and the transition of these signals can terminate the writ e. the input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
cy7c1021cv33 document #: 38-05132 rev. *d page 7 of 13 switching waveforms notes: 12. device is continuously selected. oe , ce , bhe and/or bhe = v il . 13. we is high for read cycle. 14. address valid prior to or coincident with ce transition low. read cycle no. 1 previous data valid data valid t rc t aa t oha address data out [12, 13] read cycle no. 2 (oe controlled) 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzbe t pd high oe ce icc isb impedance address data out v cc supply t dbe t lzbe t hzce bhe , ble [13, 14] current i cc i sb
cy7c1021cv33 document #: 38-05132 rev. *d page 8 of 13 notes: 15. data i/o is high impedance if oe or bhe and/or ble = v ih . 16. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. switching waveforms (continued) write cycle no. 1 (ce controlled) t hd t sd t sce t sa t ha t aw t pwe t wc bw data i/o address ce we bhe, ble [15, 16] t write cycle no. 2 (ble or bhe controlled) t hd t sd t bw t sa t ha t aw t pwe t wc t sce data i/o address bhe ,ble we ce
cy7c1021cv33 document #: 38-05132 rev. *d page 9 of 13 switching waveforms (continued) write cycle no. 3 (we controlled , low) t hd t sd t sce t ha t aw t pwe t wc t bw data i/o address ce we bhe , ble t sa t lzwe t hzwe truth table ce oe we ble bhe i/o 1 ?i/o 8 i/o 9 ?i/o 16 mode power h x x x x high-z high-z power-down standby (i sb ) l l h l l data out data out read ? all bits active (i cc ) l h data out high-z read ? lower bits only active (i cc ) h l high-z data out read ? upper bits only active (i cc ) l x l l l data in data in write ? all bits active (i cc ) l h data in high-z write ? lower bits only active (i cc ) h l high-z data in write ? upper bits only active (i cc ) l h h x x high-z high-z selected, outputs disabled active (i cc ) l x x h h high-z high-z selected, outputs disabled active (i cc ) ordering information speed (ns) ordering code package name package type operating range 8 cy7c1021cv33-8vc v34 44-lead (400-mil) molded soj commercial CY7C1021CV33-8ZC z44 44-lead tsop type ii cy7c1021cv33-8bac ba48a 48-ball fbga 10 cy7c1021cv33-10vc v34 44-lead (400-mil) molded soj commercial cy7c1021cv33-10vi industrial cy7c1021cv33-10zc z44 44-lead tsop type ii commercial cy7c1021cv33-10zi industrial cy7c1021cv33-10bac ba48a 48-ball fbga commercial cy7c1021cv33-10bai industrial
cy7c1021cv33 document #: 38-05132 rev. *d page 10 of 13 12 cy7c1021cv33-12vxc v34 lead (pb)-free 44-pin (400-mil) molded soj commercial cy7c1021cv33-12vc 44-pin (400-mil) molded soj commercial cy7c1021cv33-12vi industrial cy7c1021cv33-12ve automotive cy7c1021cv33-12zxc z44 lead (pb)-free, 44-pin tsop type ii commercial cy7c1021cv33-12zc 44-pin tsop type ii commercial cy7c1021cv33-12zi industrial cy7c1021cv33-12ze automotive cy7c1021cv33-12bac ba48a 48-ball fbga commercial cy7c1021cv33-12bai industrial cy7c1021cv33-12bae automotive 15 cy7c1021cv33-15vxc v34 lead (pb)-free, 44-pin (400-mil) molded soj commercial cy7c1021cv33-15vc 44-pin (400-mil) molded soj commercial cy7c1021cv33-15vi industrial cy7c1021cv33-15zc z44 44-pin tsop type ii commercial cy7c1021cv33-15zi industrial cy7c1021cv33-15bac ba48a 48-ball fbga commercial cy7c1021cv33-15bai industrial ordering information speed (ns) ordering code package name package type operating range
cy7c1021cv33 document #: 38-05132 rev. *d page 11 of 13 package diagrams 48-ball (7.00 mm x 7.00 mm x 1.2 mm) fbga ba48a 51-85096-*e
cy7c1021cv33 document #: 38-05132 rev. *d page 12 of 13 ? cypress semiconductor corporation, 2004. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. all products and company names mentioned in this doc ument are the trademarks of their respective holders. package diagrams (continued) 44-lead (400-mil) molded soj v34 51-85082-*b 44-pin tsop ii z44 51-85087-*a
cy7c1021cv33 document #: 38-05132 rev. *d page 13 of 13 document history page document title: cy7c1021cv33 1-mbit (64k x 16) static ram document number: 38-05132 rev. ecn no. issue date orig. of change description of change ** 109472 12/06/01 hgk new data sheet *a 115044 05/08/02 hgk ram7 version c4k x 16 async. remove ?preliminary? *b 115808 06/25/02 hgk i sb1 and i cc values changed *c 120413 10/31/02 dfp updated bga pin e4 to nc. *d 238454 see ecn rkf 1) added automotive specs to datasheet 2) added pb-free devices in the ordering information

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